Corespan Systems will exhibit at Forum Teratec 2026 on 20–21 October at the Palais des Congrès de Paris. You will find us at Stand F40.
Teratec is France's principal gathering for high-performance digital technology — manufacturers, software publishers, integrators, start-ups, laboratories and research organisations working across HPC, simulation, AI and quantum computing. It is a room full of the people who actually run these systems, which is why it matters to us.
What we are showing
DynamicXcelerator™ disaggregates GPUs and NVMe storage into pools and composes them into right-sized environments, instead of binding every resource permanently to one server configuration. Corespan Composer is the control plane that attaches and detaches those PCIe devices as requirements change — no recabling, no downtime.
Why it matters to the people buying it
An eight-GPU server is a building block, not an answer. One application needs more accelerators, another needs fewer, a third needs storage rather than compute. Buying the same fixed combination for all three is administratively convenient and a poor use of capital, power and floor space.
The alternative is to let the machine match the job. In our own lab we recently ran eight AMD Radeon AI PRO R9700s as a single fabric in a PRU 2500, holding roughly 111 GB/s bidirectional on every GPU-to-GPU pair under full-mesh load — the same silicon assignable as one large system or as several right-sized ones.
The longer argument is in What Is Old Is New Again: The Modern Mainframe Is Composable.
If you are at the show, come and find us at Stand F40, or arrange a time with the team in advance.